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low capacitance, 16- and 8-channel 15 v/+12 v i cmos ? multiplexers adg1206/ADG1207 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features <1 pc charge injection over full signal range 1.5 pf off capacitance 33 v supply range 120 on resistance fully specified at 15 v/+12 v 3 v logic-compatible inputs rail-to-rail operation break-before-make switching action 28-lead tssop and 32-lead, 5 mm 5 mm lfcsp_vq applications audio and video routing automatic test equipment data acquisition systems battery-powered systems sample-and-hold systems communication systems functional block diagrams ADG1207 s1a s8b da db s8a s1b 1-of-8 decoder a0 a1 a2 en adg1206 s1 s 16 d 1-of-16 decoder a0 a1 a2 a3 en 06119-001 figure 1. general description the adg1206 and ADG1207 are monolithic i cmos analog multiplexers comprising sixteen single channels and eight differential channels, respectively. the adg1206 switches one of sixteen inputs to a common output, as determined by the 4- bit binary address lines a0, a1, a2, and a3. the ADG1207 switches one of eight differential inputs to a common differential output, as determined by the 3-bit binary address lines a0, a1, and a2. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. when on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. the i cmos (industrial cmos) modular manufacturing process combines high voltage cmos (complementary metal- oxide semiconductor) and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no other generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased perfor- mance, dramatically lower power consumption, and reduced package size. the ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. figure 2 shows that there is minimum charge injection over the entire signal range of the device. i cmos construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments. v s (v) charge injection (pc) 1.0 0 ?15 15 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ?10 ?5 0 5 10 mux (source to drain) t a = 25c v dd = +15v v ss = ?15v v dd = +5v v ss = ?5v v dd = +12v v ss = 0v 0 6119-002 figure 2. source-to-drain charge injection vs. source voltage
adg1206/ADG1207 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 functional block diagrams............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 dual supply ................................................................................... 3 single supply ................................................................................. 5 absolute maximum ratings ............................................................7 esd caution...................................................................................7 pin configurations and function descriptions ............................8 typical performance characteristics ........................................... 12 terminology .................................................................................... 16 test circuits..................................................................................... 17 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 19 revision history 7/06revision 0: initial version
adg1206/ADG1207 rev. 0 | page 3 of 20 specifications dual supply v dd = +15 v 10%, v ss = C15 v 10%, gnd = 0 v, unless otherwise noted. 1 table 1. parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance, r on 120 typ v s = 10 v, i s = ?1 ma; see figure 28 200 240 270 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels, ?r on 3.5 typ v s = 10 v, i s = ?1 ma 6 10 12 max on resistance flatness, r flat (on) 20 typ v s = ?5 v, 0 v, +5 v; i s = ?1 ma 64 76 83 max leakage currents source off leakage, i s (off ) 0.03 na typ v d = 10 v, v s = ? 10 v; see figure 29 0.2 0.6 1 na max drain off leakage, i d (off ) 0.05 na typ v s = 1 v, 10 v; v d = 10 v, 1 v; see figure 29 0.2 0.6 2 na max channel on leakage, i d , i s (on) 0.08 na typ v s = v d = 10 v; see figure 30 0.2 0.6 2 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a typ v in = v inl or v inh 0.1 a max digital input capacitance, c in 2 pf typ dynamic characteristics 2 transition time, t transition 80 ns typ r l = 300 , c l = 35 pf 130 165 185 ns max v s = 10 v; see figure 31 t on (en) 75 ns typ r l = 300 , c l = 35 pf 95 105 115 ns max v s = 10 v; see figure 33 t off (en) 85 ns typ r l = 300 , c l = 35 pf 100 125 140 ns max v s = 10 v; see figure 33 break-before-make time delay, t bbm 20 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 10 v; see figure 32 charge injection 0.5 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 34 off isolation ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 35 channel-to-channel crosstalk ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 37 total harmonic distortion + noise 0.15 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz; see figure 38 ?3 db bandwidth adg1206 280 mhz typ r l = 50 , c l = 5 pf; see figure 36 ?3 db bandwidth ADG1207 490 mhz typ r l = 50 , c l = 5 pf; see figure 36 c s (off ) 1.5 pf typ f = 1 mhz, v s = 0 v 2 pf max f = 1 mhz, v s = 0 v c d (off ) adg1206 11 pf typ f = 1 mhz, v s = 0 v 12 pf max f = 1 mhz, v s = 0 v c d (off ) ADG1207 7 pf typ f = 1 mhz, v s = 0 v 9 pf max f = 1 mhz, v s = 0 v
adg1206/ADG1207 rev. 0 | page 4 of 20 parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments c d , c s (on) adg1206 13 pf typ f = 1 mhz, v s = 0 v 15 pf max f = 1 mhz, v s = 0 v c d , c s (on) ADG1207 8 pf typ f = 1 mhz, v s = 0 v 10 pf max f = 1 mhz, v s = 0 v power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 260 a typ digital inputs = 5 v 420 a max i ss 0.002 a typ digital inputs = 0 v, 5 v, or v dd 1.0 a max v dd /v ss 5/16.5 v min/max gnd = 0v 1 temperature range for y version is ? 40c to +125c. 2 guaranteed by design, not subject to production test.
adg1206/ADG1207 rev. 0 | page 5 of 20 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. 1 table 2. parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 300 typ v s = 0 v to10 v, i s = ?1 ma; see figure 28 475 567 625 max v dd = 10.8 v, v ss = 0 v on resistance match between channels, ?r on 5 typ v s = 0 v to 10 v, i s = ?1 ma 16 26 27 max on resistance flatness, r flat (on) 60 typ v s = 3 v, 6 v, 9 v; i s = ?1 ma leakage currents v dd = 13.2 v source off leakage, i s (off ) 0.02 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 29 0.2 0.6 1 na max drain off leakage, i d (off ) 0.05 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 29 0.2 0.6 2 na max channel on leakage, i d , i s (on) 0.08 na typ v s = v d = 1 v or 10 v; see figure 30 0.2 0.6 2 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 a typ 0.1 a max v in = v inl or v inh digital input capacitance, c in 3 pf typ dynamic characteristics 2 transition time, t transition 100 ns typ r l = 300 , c l = 35 pf 140 175 200 ns max v s = 8 v; see figure 31 t on (en) 80 ns typ r l = 300 , c l = 35 pf 100 120 130 ns max v s = 8 v; see figure 33 t off (en) 90 ns typ r l = 300 , c l = 35 pf 110 130 155 ns max v s = 8 v; see figure 33 break-before-make time delay, t bbm 25 ns typ r l = 300 , c l = 35 pf 15 ns min v s1 = v s2 = 8 v; see figure 32 charge injection 0.2 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 34 off isolation ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 35 channel-to-channel crosstalk ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz; see figure 37 ?3 db bandwidth adg1206 185 mhz typ r l = 50 , c l = 5 pf; see figure 36 ?3 db bandwidth ADG1207 300 mhz typ r l = 50 , c l = 5 pf; see figure 36 c s (off ) 1.5 pf typ f = 1 mhz, v s = 6 v 2 pf max f = 1 mhz, v s = 6 v c d (off ) adg1206 13 pf typ f = 1 mhz, v s = 6 v 15 pf max f = 1 mhz, v s = 6 v c d (off ) ADG1207 9 pf typ f = 1 mhz, v s = 6 v 11 pf max f = 1 mhz, v s = 6 v c d , c s (on) adg1206 15 pf typ f = 1 mhz, v s = 6 v 17 pf max f = 1 mhz, v s = 6 v c d , c s (on) ADG1207 10 pf typ f = 1 mhz, v s = 6 v 12 pf max f = 1 mhz, v s = 6 v
adg1206/ADG1207 rev. 0 | page 6 of 20 parameter +25c ?40c to +85c ?40c to +125c unit test conditions/comments power requirements v dd = 13.2 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 260 a typ digital inputs = 5 420 a max v dd 5/16.5 v min/max v ss = 0 v, gnd = 0 v 1 temperature range for y version is ?40c to +125c. 2 guaranteed by design, not subject to production test.
adg1206/ADG1207 rev. 0 | page 7 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog, digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first continuous current, s or d 30 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle maximum) 100 ma operating temperature ranges industrial (y version) C40c to +125c storage C65c to +150c junction temperature 150c 28-lead tssop ja , thermal impedance 97.9c/w jc , thermal impedance 14c/w 32-lead lfcsp_vq ja , thermal impedance 27.27c/w reflow soldering peak temperature (pb-free) 260(+0/?5)c 1 overvoltages at a, en, s, or d are cl amped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
adg1206/ADG1207 rev. 0 | page 8 of 20 pin configurations and function descriptions 1 v dd 28 d 2 nc 27 v ss 3 nc 26 s8 4 s16 25 s7 5 s15 24 s6 6 s14 23 s5 7 s13 22 s4 8 s12 21 s3 9 s11 20 s2 10 s10 19 s1 11 s9 18 en 12 g nd 17 a0 13 nc 16 a1 14 a3 15 a2 adg1206 top view (not to scale) nc = no connect 06119-003 nc = no connect pin 1 indicator 1 s16 2 s15 3 s14 4 s13 5 s12 6 s11 7 s10 8 s9 24 s8 23 s7 22 s6 21 s5 20 s4 19 s3 18 s2 17 s1 9 g n d 1 0 a 3 1 1 a 2 1 2 n c 1 3 n c 1 4 a 1 1 5 a 0 1 6 e n 3 2 n c 3 1 v d d 3 0 d 2 9 n c 2 8 n c 2 7 n c 2 6 n c 2 5 v s s top view (not to scale) adg1206 06119-004 figure 3. adg1206 pin configurationtssop figure 4. adg1206 pin configuration5 mm 5 mm lfcsp_vq, exposed pad tied to substrate, v ss table 4. adg1206 pin function descriptions pin number tssop lfcsp_vq mnemonic description 1 31 v dd most positive power supply potential. 2 12, 13 nc no connect. 3 26, 27, 28, 30, 32 nc no connect. 4 1 s16 source terminal 16. can be an input or an output. 5 2 s15 source terminal 15. can be an input or an output. 6 3 s14 source terminal 14. can be an input or an output. 7 4 s13 source terminal 13. can be an input or an output. 8 5 s12 source terminal 12. can be an input or an output. 9 6 s11 source terminal 11. can be an input or an output. 10 7 s10 source terminal 10. can be an input or an output. 11 8 s9 source terminal 9. can be an input or an output. 12 9 gnd ground (0 v) reference. 13 C nc no connect. 14 10 a3 logic control input. 15 11 a2 logic control input. 16 14 a1 logic control input. 17 15 a0 logic control input. 18 16 en active high digital input. when this pin is lo w, the device is disabled and all switches are turned off. when this pin is high, the ax logi c inputs determine which switch is turned on. 19 17 s1 source terminal 1. can be an input or an output. 20 18 s2 source terminal 2. can be an input or an output. 21 19 s3 source terminal 3. can be an input or an output. 22 20 s4 source terminal 4. can be an input or an output. 23 21 s5 source terminal 5. can be an input or an output. 24 22 s6 source terminal 6. can be an input or an output. 25 23 s7 source terminal 7. can be an input or an output. 26 24 s8 source terminal 8. can be an input or an output. 27 25 v ss most negative power supply potential. in si ngle-supply applicatio ns, this pin can be connected to ground. 28 29 d drain terminal. can be an input or an output.
adg1206/ADG1207 rev. 0 | page 9 of 20 table 5. adg1206 truth table a3 a2 a1 a0 en on switch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16
adg1206/ADG1207 rev. 0 | page 10 of 20 1 v dd 28 da 2 db 27 v ss 3 nc 26 s8a 4 s8b 25 s7a 5 s7b 24 s6a 6 s6b 23 s5a 7 s5b 22 s4a 8 s4b 21 s3a 9 s3b 20 s2a 10 s2b 19 s1a 11 s1b 18 en 12 gnd 17 a0 13 nc 16 a1 14 nc 15 a2 ADG1207 top view (not to scale) nc = no connect 06119-036 nc = no connect pin 1 indicator 1 s8b 2 s7b 3 s6b 4 s5b 5 s4b 6 s3b 7 s2b 8 s1b 24 s8a 23 s7a 22 s6a 21 s5a 20 s4a 19 s3a 18 s2a 17 s1a 9 g n d 1 0 a 2 1 1 n c 1 2 n c 1 3 n c 1 4 a 1 1 5 a 0 1 6 e n 3 2 n c 3 1 d b 3 0 v d d 2 9 n c 2 8 n c 2 7 d a 2 6 n c 2 5 v s s top view (not to scale) ADG1207 06119-037 figure 5. ADG1207 pin configurationtssop figure 6. ADG1207 pin configuration5 mm 5 mm lfcsp_vq exposed pad tied to substrate, v ss table 6. ADG1207 pin function descriptions pin number tssop lfcsp_vq mnemonic description 1 29 v dd most positive power supply potential. 2 31 db drain terminal b. can be an input or an output. 3 11, 12, 13 nc no connect. 4 1 s8b source terminal 8b. ca n be an input or an output. 5 2 s7b source terminal 7b. ca n be an input or an output. 6 3 s6b source terminal 6b. ca n be an input or an output. 7 4 s5b source terminal 5b. ca n be an input or an output. 8 5 s4b source terminal 4b. ca n be an input or an output. 9 6 s3b source terminal 3b. ca n be an input or an output. 10 7 s2b source terminal 2b. ca n be an input or an output. 11 8 s1b source terminal 1b. ca n be an input or an output. 12 9 gnd ground (0 v) reference. 13 26, 28, 30, 32 nc no connect. 14 C nc no connect. 15 10 a2 logic control input. 16 14 a1 logic control input. 17 15 a0 logic control input. 18 16 en active high digital input. when this pin is lo w, the device is disabled and all switches are turned off. when this pin is high, the ax logi c inputs determine which switch is turned on. 19 17 s1a source terminal 1a. can be an input or an output. 20 18 s2a source terminal 2a. can be an input or an output. 21 19 s3a source terminal 3a. can be an input or an output. 22 20 s4a source terminal 4a. can be an input or an output. 23 21 s5a source terminal 5a. can be an input or an output. 24 22 s6a source terminal 6a. can be an input or an output. 25 23 s7a source terminal 7a. can be an input or an output. 26 24 s8a source terminal 8a. can be an input or an output. 27 25 v ss most negative power supply potential. in si ngle-supply applicatio ns, this pin can be connected to ground. 28 27 da drain terminal a. can be an input or an output.
adg1206/ADG1207 rev. 0 | page 11 of 20 table 7. ADG1207 truth table a2 a1 a0 en on switch pair x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8
adg1206/ADG1207 rev. 0 | page 12 of 20 8 typical performance characteristics source or drain voltage (v) on resistance ( ? ) 200 100 0 ?18 ?15 ?12 ?9 ?6 ?3 12 15 9 06 31 180 160 140 120 80 60 40 20 t a = 25c v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v v dd = +13.5v v ss = ?13.5v 0 6119-005 figure 7. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ? ) 600 300 0 ?6 ?4 ?2 4 02 6 500 400 200 100 t a = 25c v dd = +5v v ss = ?5v v dd = +5.5v v ss = ?5.5v v dd = +4.5v v ss = ?4.5v 0 6119-006 figure 8. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ? ) 450 250 300 0 02 46 12 810 14 400 350 150 200 100 50 t a = 25c v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v v dd = 10.8v v ss = 0v 06119-007 figure 9. on resistance as a function of v d (v s ) for single supply source or drain voltage (v) on resistance ( ? ) 250 0 ?15 ?10 ?5 10 05 15 150 200 100 50 t a = +25c t a = +85c t a = +125c t a = ?40c v dd = +15v v ss = ?15v 06119-008 figure 10. on resistance as a function of v d (v s ) for different temperatures, dual supply source or drain voltage (v) on resistance ( ? ) 600 0 024 10 68 12 300 400 200 500 100 t a = +25c t a = +85c t a = +125c t a = ?40c v dd = 12v v ss = 0v 06119-009 figure 11. on resistance as a function of v d (v s ) for different temperatures, single supply temperature (c) leakage (pa) 1200 1000 800 600 400 200 0 ?200 ?400 ?600 ?800 ?1000 ?1200 02040 100 60 80 120 0 6119-010 v dd = +15v v ss = ?15v v bias = +10v/?10v i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on) + + i d , i s (on) ? ? figure 12. adg1206 leakage currents as a function of temperature, dual supply
adg1206/ADG1207 rev. 0 | page 13 of 20 temperature (c) leakage (pa) 400 ?400 ?300 ?200 ?100 0 100 200 300 02040 100 60 80 120 0 6119-011 v dd = 12v v ss = 0v v bias = 1v/10v i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , i s (on )+ + i d , i s (on) ? ? figure 13. adg1206 leakage currents as a function of temperature, single supply logic, in x (v) i dd (a) 200 60 80 100 120 140 160 180 40 20 0 0 2 4 6 8 10121416 v dd = +12v v ss = 0v v dd = +15v v ss = ?15v i dd per channel t a = 25 c 06119-012 figure 14. i dd vs. logic level v s (v) charge injection (pc) 1.0 0 ?15 15 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ?10 ?5 0 5 10 mux (source to drain) t a = 25c v dd = +15v v ss = ?15v v dd = +5v v ss = ?5v v dd = +12v v ss = 0v 0 6119-013 figure 15. source-to-drain charge injection vs. source voltage v s (v) charge injection (pc) 6 ?6 ?15 15 ?10 ?5 0 5 10 demux (drain to source) t a = 25c 4 2 0 ?2 ?4 v dd = +15v v ss = ?15v v dd = +5v v ss = ?5v v dd = +12v v ss = 0v 0 6119-014 figure 16. drain-to-source charge injection vs. source voltage 350 0 50 100 150 200 250 300 ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) v dd = +5v v ss = ?5v v dd = +12v v ss = 0v v dd = +15v v ss = ?15v 06119-050 figure 17. transition time vs. temperature frequency (hz) off isolation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m 1g v dd = +15v v ss = ?15v t a = 25c 06119-016 figure 18. off isol ation vs. frequency
adg1206/ADG1207 rev. 0 | page 14 of 20 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 1g 100m 10m 1m 100k crosstalk (db) frequency (hz) t a = 25c adjacent channels non adjacent channels 06119-051 figure 19. adg1206 crosstalk vs. frequency 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 1g 100m 10m 1m 100k crosstalk (db) frequency (hz) t a = 25c adjacent channels non adjacent channels 06119-052 figure 20. ADG1207 crosstalk vs. frequency ? 4 ?20 ?18 ?16 ?14 ?12 ?10 ?8 ?6 10k 1g 100m 10m 1m 100k on response (db) frequency (hz) v dd = +15v v ss = ?15v t a = 25c adg1206 ADG1207 06119-053 figure 21. on response vs. frequency frequency (hz) thd + n (%) 10 1 0.1 0.01 10 100 1k 10k 100k load = 10k ? t a = 25c v dd = +5v, v ss = ?5v, v s = +3.5v rms v dd = +15v, v ss = ?15v, v s = +5v rms 0 6119-020 figure 22. thd + n vs. frequency 20 0 2 4 6 8 10 12 14 16 18 ?15 15 510 0 ?5 ?10 capacitance (pf) v bias (v) v dd = +15v v ss = ?15v t a = 25c source/drain on drain off source off 06119-054 figure 23. adg1206 capacitance vs. source voltage, 15 v dual supply 20 0 2 4 6 8 10 12 14 16 18 01 810 6 4 2 capacitance (pf) v bias (v) 2 v dd = 12v v ss = 0v t a = 25c source/drain on drain off source off 06119-055 figure 24. adg1206 capacitance vs. source voltage, 12 v single supply
adg1206/ADG1207 rev. 0 | page 15 of 20 12 0 2 4 6 8 10 ?15 15 510 0 ?5 ?10 capacitance (pf) v bias (v) v dd = +15v v ss = ?15v t a = 25c source/drain on drain off source off 06119-056 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 100 10m 1m 100k 10k 1k ac psrr (db) frequency (hz) t a = 25c no decoupling capacitors v dd = +15v v ss = ?15v v p-p = 0.63v 06119-058 figure 25. ADG1207 capacitance vs. source voltage, 15 v dual supply figure 27. ac psrr vs. frequency 14 12 0 2 4 6 8 10 01 810 6 4 2 capacitance (pf) v bias (v) 2 v dd = 12v v ss = 0v t a = 25c source/drain on drain off source off 06119-057 figure 26. ADG1207 capacitance vs. source voltage, 12 v single supply
adg1206/ADG1207 rev. 0 | page 16 of 20 terminology r on ohmic resistance between d and s. r on difference between the r on of any two channels. r flat(on) flatness is defined as the difference between the maximum and minimum value of on resistance as measured. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminals d and s. c s (off) channel input capacitance for the off condition. c d (off) channel output capacitance for the off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and the switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and the switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t bbm off time measured between the 80% points of the switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. i dd positive supply current. i ss negative supply current. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. thd + n the ratio of the harmonic amplitude plus noise of the signal to the fundamental. acpsrr (ac power supply rejection ratio) measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p-p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsrr.
adg1206/ADG1207 rev. 0 | page 17 of 20 test circuits i ds sd v s v 06119-025 sd v s a a v d i s (off) i d (off) 06119-026 sd a v d i d (on) nc nc = no connect 06119-027 figure 28. on resistance figure 29. off leakage figure 30. on leakage 3v 0v output t r < 20ns t f < 20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output adg1206 1 50? 300 ? gnd s1 s2 to s15 s16 d 35pf v in 2.4v en v dd v ss v dd v ss v s1 v s16 1 similar connection for ADG1207. a0 a2 a1 a3 06119-028 figure 31. address to ou tput switching times, t transition 3v 0v output 80% 80% a ddress drive (v in ) t bbm output adg1206 1 50? 300? gnd s1 s2 to s15 s16 d 35pf v in 2.4v en v dd v ss v dd v ss v s 1 similar connection for ADG1207. a0 a2 a1 a3 06119-029 figure 32. break-before-make delay, t bbm 3v 0v output 50% 50% t off (en) t on (en) 0.9v o 0.9v o enable drive (v in ) output adg1206 1 300? gnd s1 s2 to s16 d 35pf 50? v in en v dd v ss v dd v ss v s 1 similar connection for ADG1207. a0 a2 a1 a3 06119-030 figure 33. enable delay, t on (en), t off (en)
adg1206/ADG1207 rev. 0 | page 18 of 20 3v v in v out q inj = c l v out v out v in adg1206 1 gnd v dd v ss v dd v ss 1 similar connection for ADG1207. a0 d c l 1nf v out a2 a1 a3 s en r s v s 06119-031 figure 34. charge injection v out 50 ? network analyzer r l 50? s d 50? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 0 6119-032 figure 35. off isolation v out 50? network analyzer r l 50 ? s d v s v dd v ss 0.1f v dd 0.1f v ss gnd insertion loss = 20 log v out with switch v out without switch 06119-033 figure 36. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 06119-034 figure 37. channel-to-channel crosstalk v out r s audio precision r l 10k ? in v in s d v s v p-p v dd v ss 0.1f v dd 0.1f v ss gnd 06119-035 figure 38. thd + noise
adg1206/ADG1207 rev. 0 | page 19 of 20 outline dimensions compliant to jedec standards mo-153-ae 28 15 14 1 8 0 seating plane c oplanarit y 0.10 1.20 max 6.40 bsc 0.65 bsc pin 1 0.30 0.19 0.20 0.09 4.50 4.40 4.30 0.75 0.60 0.45 9.80 9.70 9.60 0.15 0.05 figure 39. 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters * compliant to jedec standards mo-220 with exception to paddle orientation. 0.30 0.23 0.18 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 max 0.85 nom seating plane coplanarity 0.05 1 32 8 9 25 24 16 17 bottom view 2.85 2.70 sq 2.55 0.50 0.40 0.30 0.60 0.42 0.24 0.60 0.42 0.24 3.50 ref 0.50 bsc pin 1 indicator 5.00 bsc sq 4.75 bsc sq 0.45 bsc 0.20 min * exposed pad (top view) figure 40. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model temperature range description package option adg1206yruz 1 ?40c to +125c 28-lead thin shrink small outline package [tssop] ru-28 adg1206yruz-reel7 1 ?40c to +125c 28-lead thin shrink small outline package [tssop] ru-28 adg1206ycpz-reel7 1 ?40c to +125c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 ADG1207yruz 1 ?40c to +125c 28-lead thin shrink small outline package [tssop] ru-28 ADG1207yruz-reel7 1 ?40c to +125c 28-lead thin shrink small outline package [tssop] ru-28 ADG1207ycpz-reel7 1 ?40c to +125c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-2 1 z = pb-free part.
adg1206/ADG1207 rev. 0 | page 20 of 20 notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06119-0-7/06(0)

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